MIPI display pannel

When I was introduced to the project the display was not at all working. We were doing the porting of Froyo kernel(2.6.32) for garnett phone.

Let me first describe how a MIPI pannel driver works. Mobile Industry Processor Interface(MIPI) alliance is about setting up a standard for interfacing the processor with different peripherals. Our concern in this context is about Display Interface. The Display Serial Interface defines protocol between processor and peripheral device using a D-PHY physical interface. It is build by adopting pixel format and command set specified in DPI-2(Display Parallel Interface) and DCS standards. DSI serializes all pixel data, command and events. The legacy interfaces convey the data and control to and from from the peripheral on a parallel bus. The unavoidable consequence of this transformation is the increased latency. But the D-PHY solution brings out the very low power consumption.

The practical data rate per lane is <1Gb/s.
Min no of pins per direction 4.

So that's it about the DSI interface.

Now on the Garnet phone, which uses the Sam-sung Humming bird processor(C110) has 3-D accelerator. There is a separate driver for this hardware accelerator. In our display driver we will allocate the memory for the frame buffer and pass it to the hardware accelerator driver. It will decode the frames and place it in the frame buffer memory. From Frame buffer memory, the DSIM(Display serial interface Module) implements the DSI protocol for sending data to the lcd panel. The lcd panel used was an AMOLED.

The LCD panel interrupts the processor whenever it is ready to receive a new frame. So initially this gpio pin was not configured properly. After fixing this display started working after booting up. But boot animation was not showing.

The code base for Garnett is taken from the galaxy S phone. Later we found out from some status register that the DSIM controller is going in to ULPS(Ultra Low Power State). On Samsung galaxy, usb OTG uses a LDO3 for USB_V1.1 voltage supply. But on Garnett, this LDO is shared between USV_V1.1 and MIPI_PowerEN. Unluckily usb code was disabling the LDO3 during boot-up.

But still display didn't leave me. The problem becomes like this now. Some times boot animation is not coming. Hmm... What to do... Have to continue hunting... I dumped all the registers of the C110 processor(clock, DSIM, video controllor registers) using JTAG. Everything seems fine. Then checked the gpio mux settings. No issues there also. Cannot find direction to move ahead. At the end, problem was due to frame buffer probe is called before the regulator framework is initialized. During the regulator initialization he reset the chip and enables all the voltage again. So sometimes the LCD panel is going into invalid state.

So good lesson learned. Even if the boot loader initialize the regulators or not, we have to bring regulator up and stabilize all the voltages before initializing any of the peripherals. Dammn it!!!!. Thought of doing this first but didn't contemplate on this much.