SMP bit affects L1 cache operation on Cortex-A9 MPCore

Q) We have a region which innercacheble with Write back write allocate and SMP bit is set. So if we update this region with some data it's updating in cache, main memory is not updated, which is as expected. 

But if we clear the SMP bit and update this region then the data is getting updated to external memory not getting updated in Cache. Please not all these operation is from core0, core1 is in WFI during this and it's SMP bit is not set.

Ans) This information is contained in the ARM Architecture Reference Manual with the TRM for the Cortex-A9 MPCore and the Cortex-A9 TRM offering additional information.

When an area of memory is declared as Normal, Write-back and shareable with the processor operating in SMP mode, the data will be cached.  At this point the SCU will effectively ensure that the data shared between the processors in SMP mode is managed to maintain coherency.

However, when you leave SMP the shareable attribute tells the MMU that this data is shared amongst devices and this overrides the cache attributes and is treated as non-cacheable.  This is explained in section 4.3.10, Auxiliary Control Register of the Cortex-A9 TRM.  This is consistent with the behaviour that you're observing.